1. Field of the Invention
The present invention relates to a flash memory device, and more particularly, to a flash memory device including a data buffer, and a programming method of the same.
2. Description of the Related Art
Semiconductor memory devices are classified as either volatile semiconductor memory devices or non-volatile semiconductor memory devices. Volatile semiconductor memory devices have high read and write operation speeds, but lose their data when power supply is stopped. Non-volatile semiconductor memory devices retain their data even without power. Therefore, non-volatile semiconductor memory devices are used to store data that must be preserved regardless of power supply. A flash memory, such as a flash electrically erasable programmable read-only memory (EEPROM), which is one type of nonvolatile semiconductor memory device, is particularly advantageous for use as a large-capacity secondary memory device because of its high degree of integration.
Flash memories are classified as either NAND type flash memories or NOR type flash memories. The NAND flash memories perform write operations (hereinafter, referred to as program or programming operations) and erase operations by Folwer-Nordheim tunneling (F-N tunneling). The NOR flash memories perform program operations by hot-electron injection, and erase operations by F-N tunneling. The NOR flash memories are code storage type memories, and are commonly used for devices that require high-speed data processing because of their high operation speeds.
A cell array of a NOR flash memory includes multiple banks, where each bank includes multiple sectors, and each sector includes multiple memory cells. In general, in the NOR flash memory, the erase operation is performed for each sector, and the program operation is performed for multiple words (or for each byte).
In response to demands for a low-cost and high-density flash memory, a multi-level cell (MLC) technology is being used instead of a single-level cell (SLC) technology. In the MLC technology, multiple bits of data, i.e., multiple states (e.g., 00, 10, 01, 00), can be stored in each memory cell, while in the SLC technology, a single bit of data, i.e., two states (e.g., 0, 1), can be stored in each memory cell.
In the MLC technology, one cell must be able to store multiple states. Since different programming is performed for each state of the MLC, precise programming control of each state is required. Consequently, an MLC flash memory requires more time for programming memory cells than an SLC flash memory. To address this problem, a buffer programming method may be used. In the buffer programming method, a data buffer receives and stores program data corresponding to N words (N is a positive integer), and performs a scan operation and a program operation on stored data.
In general, to perform a program operation in a flash memory, a corresponding address must be pre-erased (i.e., data must be made into 1 (or 11)). Thus, when program data is 1 (or 11), it can be assumed that the desired data has already been programmed even though no program operation has been performed. Thus, according to the buffer programming method, data 0 (or 00, 01, 10), which is to be actually programmed, is retrieved by scanning the data stored in the data buffer. The retrieved data are programmed simultaneously in sets of a predetermined number of bits.
FIG. 1 is a view showing an exemplary configuration of a data buffer storing data corresponding to N words.
Referring to FIG. 1, an address configuration of the data buffer is physically fixed, corresponding to an address configuration of data to be stored in the data buffer. For example, each column address of the data to be stored determines a word region of the data buffer where the data are stored. The data stored in the data buffer have respective sequential addresses. When an address of the first data (hereinafter, referred to as a first data address) of the data to be stored in the data buffer corresponds to the 10th word region of the data buffer, for example, the data are stored sequentially from the 10th word region of the data buffer to an Nth word region of the data buffer.
FIG. 2 is a view illustrating a general data storage example of storing program data in an N-word data buffer. Specifically, in FIG. 2, program data are stored in a 32-word data buffer.
Referring to FIG. 2, even when the data to be programmed (program data PGM_DATA) are consecutive data and correspond to 32 words, all of the program data PGM_DATA are not simultaneously stored in the data buffer due to the address configuration. For example, when a first data address 1st_ADD of the consecutive program data PGM_DATA corresponds to a 21st word region ADD 20 of the data buffer, the program data PGM_DATA are stored in the data buffer from the 21st word region ADD 20 to a 32nd word region ADD 31 (refer to part “A” of FIG. 2). Then, after the program data stored in the data buffer are programmed (e.g., written to a memory cell array), the remaining program data PGM_DATA are stored in the data buffer from a first word region ADD 0 to a 20th word region ADD 19 (refer to part “B” of FIG. 2). Thus, even though the program data PGM_DATA have 32 words with consecutive addresses, the program data PGM_DATA are divided into two groups, part A and part B, and are separately stored because of a limited physical address boundary of the data buffer. Further, the two separate groups of data are then programmed independently, which increases a programming time.